Portapack-Carnage

◆ RCC_CFGR_PLLXTPRE_PREDIV1_Div2 [3/3]

#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2   ((uint32_t)0x00020000)

#include <firmware/chibios/os/hal/platforms/STM32F30x/stm32f30x.h>

PREDIV1 clock divided by 2 for PLL entry